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DSP56371 Overview
the DSP56300 family of programmable CMOS DSPs. The DSP56371 is targeted to applications that
require digital audio compression/decompression, sound field processing, acoustic equalization and other
digital audio algorithms. Changes in core functionality specific to the DSP56371 are also described in this
manual. See Figure 1. for the block diagram of the DSP56371.
5
2
12
12
11
Memory Expansion Area
SHI
Interface
Triple
Timer
ESAI ESAI_1
Interface Interface
GPIO
EFCOP
Program
X Data
Y Data
RAM
4K × 24
RAM
36K × 24
RAM
48K × 24
2
DAX
Peripheral
ROM
64K × 24
ROM
32K × 24
ROM
32K × 24
Expansion Area
Address
Generation
Unit
Six Channel
DMA Unit
Bootstrap
ROM
Internal
Data
Bus
Switch
YAB
XAB
PAB
DAB
24-Bit
DSP56300
Core
DDB
YDB
XDB
PDB
GDB
Power
Clock
Gen-
erator
PLL
Program
Interrupt
Controller
Program
Decode
Controller
Program
Address
Generator
Data ALU
24 × 24 + 56 → 56 - bit MAC
Two 56-bit Accumulators
Mgmt .
JTAG
OnCE ?
4
56-bit Barrel Shifter
MODA / IRQA
EXTAL
RESET
PINIT/NMI
MODB/IRQB
MODC/IRQC
MODD/IRQD
Figure 1. DSP56371 Block Diagram
2.2
DSP56300 Core Description
The DSP56371 uses the DSP56300 core, a high-performance, single clock cycle per instruction engine that
provides up to twice the performance of Motorola's popular DSP56000 core family while retaining code
compatibility with it.
DSP56371 Data Sheet, Rev. 4.1
2
Freescale Semiconductor
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